PhD in Quality-of-Service-Aware Architectures for Shared Memory Chiplets in Multi-Die Systems at imec – Germany

Summary

The advertised PhD position at imec focuses on developing Quality-of-Service‑aware shared‑memory chiplet architectures for safety‑critical, especially automotive, systems. The researcher will design scalable architectures, evaluate and benchmark system performance, develop RTL models, and conduct literature reviews. The work involves QoS‑aware interconnects, memory scheduling, traffic prioritization, and resource partitioning, using system‑level simulation and architectural modeling. The role is full‑time, based in Heilbronn, Germany, and reports to a daily advisor with a professor as promoter. Applicants must hold a Master’s degree in electrical engineering, computer science, or a related field, possess a solid foundation in processors and chiplet design, be familiar with cache coherence, and have experience with VHDL/Verilog/SystemVerilog. Good English proficiency is required. The deadline for applications is 24 October 2026.

Key Facts

Department	Advanced Chip Design Accelerator (ACDA)
Position Type	PhD researcher
Discipline	Electrical engineering, computer science, or related field
Research Area	Quality-of-Service-Aware Architectures for Shared Memory Chiplets in Multi-Die Systems
Degree Required	Master’s degree in electrical engineering, computer science, or a related field
Language	English
Deadline	2026-10-24
Employer Contact	[email protected]

About the Project

The project aims to create scalable shared‑memory chiplet architectures that guarantee predictable performance and Quality‑of‑Service for safety‑critical applications, particularly in the automotive sector. It will explore how compute chiplets share memory resources while managing contention, latency, and bandwidth across on‑chip networks, die‑to‑die links, and memory controllers. Key activities include QoS‑aware interconnect design, memory scheduling, traffic prioritization, resource partitioning, architectural modeling, and system‑level simulation, supported by extensive benchmarking and RTL development.

Key Responsibilities

• Architecture design (30%)
• System evaluation and benchmarking (30%)
• RTL development and modeling (30%)
• Literature review (10%)
• Investigate QoS‑aware interconnects and memory scheduling
• Perform traffic prioritization and resource partitioning studies
• Conduct architectural modeling and system‑level simulation

Required Skills

• Solid foundation in processors, compute systems, and chiplet architecture
• Familiarity with cache coherence
• Experience with VHDL, Verilog, or SystemVerilog
• Understanding of RTL modeling and simulation
• Interest in hardware/software co‑design and optimization
• Good English proficiency

Who Should Apply

Candidates with a Master’s degree in electrical engineering, computer science, or a related discipline, who have a solid background in processors and chiplet architectures, are familiar with cache coherence, and have hands‑on experience with VHDL, Verilog or SystemVerilog. Applicants should be interested in hardware/software co‑design, QoS‑aware systems, and possess good English communication skills.

About the Employer

imec is seeking a PhD researcher to develop scalable shared‑memory chiplet architectures with QoS guarantees for safety‑critical, especially automotive, applications. The position is within imec’s Advanced Chip Design Accelerator (ACDA) located in Heilbronn, Germany. The role is full‑time and reports to a daily advisor, with a professor from the Technical University of Munich acting as promoter.

Frequently Asked Questions

What is the application deadline?

The deadline is 24 October 2026.

Where is the position located?

Heilbronn, Germany.

What degree is required?

A Master’s degree in electrical engineering, computer science, or a related field.

How many positions are available?

One position.

Who can I contact for more information?

Email [email protected].

What language proficiency is needed?

Good English is required.